An Algorithm for FPGA based Implementation of Variable Precision MAC unit for High Performance Digital FIR Filters

K. Neelima; M. Bharathi

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An Algorithm for FPGA based Implementation of Variable Precision MAC unit for High Performance Digital FIR Filters

机译：基于FPGA的高性能数字FIR滤波器可变精度MAC单元实现的算法。

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The MAC Unit plays an important role in DSP applications. When implemented on FPGA, many MAC Units can be implemented on a single FPGA flexible to different design architectures. Hence the need of efficient MAC Units arises for filter applications. This paper discusses about variable precision based MAC Unit implemented on FPGA at algorithmic level. The proposed algorithm for FIR Filters is high performance and area efficient than the conventional MAC Unit. The delay for VP MAC Unit is reduced nearly by 60% than the conventional MAC Unit

机译：MAC单元在DSP应用中起着重要作用。当在FPGA上实现时，许多MAC单元可以在单个FPGA上实现，以适应不同的设计架构。因此，对于滤波器应用，需要有效的MAC单元。本文在算法层面讨论了在FPGA上实现的基于可变精度的MAC单元。所提出的FIR滤波器算法比常规MAC单元具有更高的性能和面积效率。 VP MAC单元的延迟比传统MAC单元减少了近60％

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《International Journal of Engineering Research and Applications》 |2012年第6期|共3页
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K. Neelima; M. Bharathi;
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2. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm [J] . Tsao Y.-C. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2012,第6期

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3. PERFORMANCE ANALYSIS OF DIGITAL FIR LP FILTER IMPLEMENTATION BASED ON 5 WINDOW TECHNIQUES: RECTANGULAR, BARLETT, HANN, HAMMING AND BLACKMAN [J] . Vorapoj Patanavijit International journal of simulation: systems, science and technology . 2019,第3期

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4. Alternative approaches implementing high-performance FIR filters onlookup-table-based FPGAs: a comparison, [C] . Tien-Toan Do, Univ. of Hannover, Hannover, Configurable Computing: Technology and Applications . 1998

机译：在基于查询表的FPGA上实现高性能FIR滤波器的替代方法：
5. Multiplierless CSD techniques for high performance FPGA implementation of digital filters. [D] . Wang, Yunhua. 2007

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6. Design of efficient circularly symmetric two-dimensional variable digital FIR filters [O] . Thayyil Bindima, Elizabeth Elias 2016

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7. FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating [O] . A. Senthilkumar, A. M. Natarajan 2008

机译：减少过渡流水线可变精度门控的功率感知FIR滤波器的FPGA实现

An Algorithm for FPGA based Implementation of Variable Precision MAC unit for High Performance Digital FIR Filters

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