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首页> 外文期刊>International Journal of Engineering Research and Applications >Self-controllable Voltage Level Technique to reduce leakage current in DRAM 4×4
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Self-controllable Voltage Level Technique to reduce leakage current in DRAM 4×4

机译：自控电压电平技术可减少DRAM 4×4中的泄漏电流

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摘要

As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology The present work shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique. SVL technique is leakage current reduction technique. Simulation is done by using a micro wind 3.1 and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.
机译：随着技术的改进以支持非常大的芯片尺寸，系统设计人员面临功耗问题和泄漏电流问题。 CMOS技术的重要性已提高到现在已成为主导VLSI技术的核心地位。本工作显示了具有自控电压电平（SVL）技术的DRAM 4×4（动态随机存取存储器）的实现。 SVL技术是降低漏电流的技术。通过使用微风3.1和DSCH 2进行仿真。通过在4×4 DRAM中使用SVL技术，可以减少37％的泄漏电流。

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