Error Correcting Codes are required to have a reliable communication through a medium that has an unacceptable bit error rate and low signal to noise ratio. Data gets corrupted during the transmission and reception due to noises and interferences. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are being widely used in variety communication and storage systems. In this paper, a simplified algorithm for BCH decoding is proposed with a view to reduce the number of iterations for error detection in the syndrome calculator block of BCH decoders with a percentage of up to 80 % compared to the basic syndrome block. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of syndrome block on FPGA card.
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