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Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

机译：VLSI电路中的亚阈值漏电流降低技术-综述

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There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
机译：对由电池供电的便携式设备的需求不断增长，这导致半导体技术制造商缩小了功能尺寸，从而降低了阈值电压，并在单个芯片上实现了复杂的功能。通过缩小特征尺寸，动态功耗不起作用，但是静态功耗变得等于或大于动态功耗。因此，在最近的CMOS技术中，静态功耗，即由于漏电流引起的功耗，已成为VLSI芯片设计人员的挑战所在。为了延长电池寿命并保持电路的可靠性，降低漏电流是主要目标。本文讨论了用于减少亚阈值泄漏的技术的基本概述。根据调查的技术，一种方法是

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