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DL(2m): A New Scalable Interconnection Network for System-on-Chip

机译:DL(2M):用于片上系统的新可扩展互连网络

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—With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of System-on-Chip(SoC) design. Network-on-Chip(NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. Focusing on decreasing node degrees, reducing links and reusing router nodes, a regular NoC architecture, named Double-Loop(DL(2m)) interconnection network, is proposed. The topology of DL(2m) is simple, symmetric and scalable in architecture, and it is 3-regular plane graph with 4m nodes. The nodes of DL(2m) adopt Johnson coding scheme that can make the design of routing algorithms simple and efficient. The DL(2m) was compared with Ring and 2D Mesh by simulating and analysing, both under uniform load and under more realistic load assumptions in the several network size scenarios. The results show that the DL(2m) topology is a good trade-off between performance and cost, and it is a better NoC topology when there are not too many network nodes.
机译:- 为半导体技术的特征大小减少和智能性质(IP)核心增加,芯片通信架构对芯片系统(SoC)设计的性能和面积产生了很大的影响。已提出芯片上网(NOC)作为复杂的SOC通信问题的有希望的解决方案,并已被学术界和工业广泛接受。专注于节点度降低,还原链路和重用路由器节点,常规NOC架构,名为双环(DL(2M))互连网络。 DL(2M)的拓扑在架构中简单,对称和可扩展,并且是具有4M节点的3常规平面图。 DL(2M)的节点采用了约翰逊编码方案,可以使路由算法简单有效地设计。通过模拟和分析,在均匀负载下和在几个网络尺寸方案中的更现实的负载假设下,将DL(2M)与环和2D网格进行比较。结果表明,DL(2M)拓扑是性能和成本之间的良好权衡,并且当没有太多网络节点时,它是一个更好的NOC拓扑。

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