—This paper proposes a System-on-Programmable-Chip (SoPC) architecture to implement a stereo matchingalgorithm based on the sum of absolute differences (SAD) ina FPGA chip which can provide 1396×1110 disparity mapsat 30 fps speed. The hardware implementation involves a 32-bit Nios II microprocessor, memory interfaces and stereomatching algorithm circuit module. The stereo matchingalgorithm core is modeled by the Matlab-based DSP Builder.The system can process many different sizes of stereo pairimages through a configuration interface. The maximumhorizon resolution of stereo images is 2048.
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