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首页> 外文期刊>Facta Universitatis. Series Electronics and Energetics >FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING
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FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING

机译：强制堆栈睡眠晶体管（Fortran）：基于CMOS的电路设计中的一种新的漏电流减少方法

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摘要

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
机译：泄漏电流的降低已成为基于纳米技术的低功耗，低电压和高性能VLSI应用的重要问题。本研究制品讨论了一种新的低功耗电路设计FORTRAN（强制堆栈沉睡晶体管）的方法，这降低了VLSI域的基于CMOS的电路轮廓中的漏功率效率。 Fortran方法可减少有效的漏电流以及待机操作模式。此外，当电路从活动模式到待机模式和反之亦然时，它不是时光。为了验证所提出的设计方法，实验在导师图形捆绑的Tanner EDA工具上进行了预计的电路设计，用于满加法器，4逆变器链和4位乘数设计，利用180nm，130nm和90nm TSMC技术的4位乘数设计节点。所获得的结果表明，泄漏功率的95-98％至关重要降低的结果，并且动态功率降低了15-20％，延迟轻微增加。将结果结果进行比较，以准确性，具有可用于主动和待机操作模式的显着设计方法。

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