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首页> 外文期刊>IEEE Transactions on Dielectrics and Electrical Insulation >A modular and compact long pulse modulator based on the SML topology for the ESS Linac
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A modular and compact long pulse modulator based on the SML topology for the ESS Linac

机译：基于SML拓扑的ESS Linac模块化且紧凑的长脉冲调制器

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摘要

The ESS Linac project, phase I, requires 12 long pulse klystron modulators with compact footprint, high pulse power and improved quality both on the output pulse waveform and on the input AC power line. Conventional long pulse modulators are typically based on HV pulse transformers and commonly exhibit poor efficiency, low power density, large footprint and cost, with still limited performance on pulse rise time, pulse flat-top accuracy and AC power line quality (flicker, current harmonic distortion, power factor). This paper presents the Stacked Multi-Level (SML) klystron modulator topology, a novel modular concept based on the association of several HV modules in series at their output, each formed by a high voltage and high-frequency transformer, a HV diode rectifier bridge and a low pass filter. Each HV module is fed from a low voltage power electronic inverter at ground potential since the transformer provides the required galvanic isolation between primary and secondary windings. This topology is believed to better suit the application and better satisfy ESS requirements, directly addressing the mentioned shortcomings of conventional topologies. The development and validation of this new concept has included the design and construction of a reduced scale prototype with the potential of delivering long (3.5 ms) and high quality pulses (0-99% rise time <;120 μs and flat top ripple <;0.15%) with pulse amplitudes up to 115 kV and pulse power up to 2 MW, while maintaining excellent AC grid power quality (low flicker operation <; 0.2%, sinusoidal current absorption with total harmonic distortion <; 3%, and unitary power factor). The paper describes the main features of the topology and the main design aspects, presenting results both from simulation models, including parasitic elements, and from an experimental setup.
机译：ESS Linac项目的第一阶段需要12个长脉冲速调管调制器，它们在输出脉冲波形和输入交流电源线上都具有紧凑的占位面积，高脉冲功率和更高的质量。常规的长脉冲调制器通常基于HV脉冲变压器，通常显示效率低，功率密度低，占用空间大和成本低，但脉冲上升时间，脉冲平顶精度和交流电源线质量（闪烁，电流谐波）的性能仍然有限失真，功率因数）。本文介绍了堆叠式多级（SML）速调管调制器拓扑，这是一种新颖的模块化概念，其基于在输出端串联了几个高压模块的关联，每个高压模块均由高压和高频变压器，高压二极管整流桥组成和低通滤波器。每个HV模块均由处于地面电位的低压功率电子逆变器供电，因为变压器可在初级绕组和次级绕组之间提供所需的电流隔离。该拓扑被认为更适合于应用并且更好地满足ESS要求，直接解决了常规拓扑的上述缺点。这个新概念的开发和验证包括设计和构造一个缩小规模的原型，该原型具有提供长（3.5 ms）和高质量脉冲（0-99％上升时间<; 120μs和平坦顶部纹波<; 0.15％），脉冲幅度高达115 kV，脉冲功率高达2 MW，同时保持了出色的交流电网电能质量（低闪变<; 0.2％，正弦电流吸收，总谐波失真<; 3％，单位功率因数） ）。本文介绍了拓扑的主要特征和主要设计方面，并给出了包括寄生元件在内的仿真模型以及实验装置的结果。

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