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THE PROTOTYPE COMES OF AGE

机译：原型时代的来临

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Over the past few years, interest in prototyping electronic designs has grown. The rising size and complexity of systems and the limitations of using a single-purpose model-the hardware-design model-have fueled this growth. Engineers have traditionally modeled the hardware-design model at the RTL (register-transfer level) and then performed a number of refinement steps until that model becomes the implementation model. This single-purpose model has in the past found use only in hardware design, although engineers are now considering its use for other purposes. The EDA industry has developed tools, such as equivalence checkers, to ensure that the functionality of this evolving model stays consistent during these transformations. In an ideal world, all modifications would apply to the single model at the start of the chain, and changes would propagate throughout the chain. In the real world, however, engineers make changes to the subsequently derived models, potentially leading to departures between the original high-level model and the final implementation. This area has always been regarded as a risk in the development cycle, and that risk increases as additional independent models are generated throughout the flow.
机译：在过去的几年中，对电子设计原型的兴趣不断增长。系统规模和复杂性的不断提高以及使用单一用途模型（硬件设计模型）的局限性推动了这一增长。工程师传统上在RTL（寄存器传输级别）上对硬件设计模型进行建模，然后执行许多优化步骤，直到该模型成为实现模型为止。过去，尽管工程师现在正在考虑将其用于其他目的，但这种单一用途的模型仅在硬件设计中使用。 EDA行业已经开发了工具，例如等效性检查器，以确保在这些转换过程中，这种不断发展的模型的功能保持一致。在理想情况下，所有修改都将在链的开头应用于单个模型，并且更改将在链中传播。但是，在现实世界中，工程师会对后续衍生的模型进行更改，从而可能导致原始的高级模型与最终的实现方案之间出现偏差。在开发周期中，该区域一直被视为风险，并且随着流程中其他独立模型的产生，该风险会增加。

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  • 来源
    《Electrical Design News》 |2012年第1期|p.30-34|共5页
  • 作者

    BRIAN BAILEY;

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  • 收录信息 美国《科学引文索引》(SCI);
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  • 正文语种 eng
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