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首页> 外文期刊>IEEE Transactions on Electron Devices >Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes
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Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

机译：低压CMOS工艺负电压电源引脚的高压容耐电源轨ESD保护电路设计

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摘要

In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of -6 V has been proposed and verified in a 0.18- $mu ext{m}$ 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this -6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of $400mu ext{m}$ can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of 5.4 nA at room temperature under the circuit operating condition with -6-V supply voltage.
机译：在植入的生物医学器件中，具有广泛应用了具有单极刺激设计的硅芯片。为了保护植入硅芯片的负电压销从静电放电（ESD）损坏，应仔细设计ESD保护电路，以避免使用负电压的正常电路操作下的任何错误的电流路径。在本文中，已经提出了一种新的电源导轨ESD钳钳电路，用于应用-6V的工作电压，并以0.18-$ mu text {m} $ 3.3-v CMOS进程验证。用仅3.3V NMOS / PMOS器件实现的提出的电路，能够防止在-6-V应用下进行栅极氧化物可靠性问题。利用所提出的ESD检测电路，可以大大提高主ESD钳位装置的开启速度，即堆叠-NMOS（STNMOS）。宽度为400美元 mu text {m} $的STNMO可以维持超过8 kV人体模型（HBM）ESD应力，并在室温下在电路运行条件下执行5.4天的低待机漏电流为-6- v电源电压。

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