Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

Gola Deepti; Singh Balraj; Srinivas P. S. T. N.; Tiwari Pramod Kumar

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Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

机译：Trigate连接晶体管的热噪声模型，包括基板偏置效应

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Thermal noise power spectral density (PSD) models for trigate junctionless field-effect transistors (TG-JLFETs) incorporating substrate bias effects are developed in this article. The PSDs of drain current thermal noise, induced gate noise, and cross correlation between the two noises are derived for TG-JLFET using the modified Klaassen and Prins (KP) equation. An all-region drain current model of TG-JLFET is used to obtain the aforementioned thermal noises. Thermal noise PSD in TG-JLFET depends on channel conductance, and substrate bias voltage significantly modulates the channel conductance, and thus, the substantial impact of substrate bias can be observed on thermal noise of TG-JLFET. Model results are validated with the simulation results obtained using a 3-D technology computer-aided design (TCAD)-based device simulator from Synopsys.

机译：在本文中开发了一种具有底物偏压效应的Trace接线场效应晶体管（TG-JLFET）的热噪声功率谱密度（PSD）模型。使用改进的Klaassen和Prins（KP）方程，推导出漏极电流热噪声，诱导栅极噪声和两个噪声之间的互相关的PSD。使用TG-JLFET的全区域漏极电流模型来获得上述热噪声。 TG-JLFET中的热噪声PSD取决于通道电导，并且基板偏置电压显着调制通道电导，因此，可以在TG-JLFET的热噪声上观察到基板偏置的显着影响。模型结果验证了使用Synopsys使用三维技术计算机辅助设计（TCAD）的设备模拟器获得的模拟结果。

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来源
《IEEE Transactions on Electron Devices》 |2020年第1期|263-269|共7页
作者
Gola Deepti; Singh Balraj; Srinivas P. S. T. N.; Tiwari Pramod Kumar;
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作者单位

IIT Patna Dept Elect Engn Patna 801103 Bihar India;

GB Pant Inst Engn & Technol Dept Elect & Commun Engn Pauri 246194 India;

IIT Patna Dept Elect Engn Patna 801103 Bihar India;

IIT Patna Dept Elect Engn Patna 801103 Bihar India;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Thermal noise; Mathematical model; Substrates; Logic gates; MOSFET; Solid modeling; Junctionless field-effect transistor (JLFET); noise modeling; substrate bias; thermal noise; trigate (TG);

机译：热噪声;数学模型;基板;逻辑门;MOSFET;实体建模;无连接场效应晶体管（JLFET）;噪声模型;衬底偏置;热噪声;TRIGE噪音;

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1. A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects [J] . Deepti Gola, Balraj Singh, Pramod Kumar Tiwari IEEE Transactions on Electron Devices . 2017,第9期

机译：包含衬底偏置效应的三栅极无结型场效应晶体管的阈值电压模型
2. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization [J] . Doria Rodrigo Trevisoli, Trevisoli Renan, de Souza Michelly, Microelectronic Engineering . 2017,第juna期

机译：通过低频噪声表征分析衬底偏置对无结纳米线晶体管中界面俘获电荷的影响
3. Effects of Substrate Bias on Low-Frequency Noise in Lateral Bipolar Transistors Fabricated on Silicon-on-Insulator Substrate [J] . Hu Qitao, Chen Si, Zhang Shi-Li, IEEE Electron Device Letters . 2020,第1期

机译：硅 - 绝缘基板上横向双极晶体管中衬底偏置对低频噪声的影响
4. Investigation of Thermal Noise in Trigate Junctionless Transistor [C] . Deepti Gola, Balraj Singh, Pramod Kumar Tiwari International Conference on Electrical, Electronics and Computer Engineering . 2019

机译：Trigate无结晶体管的热噪声研究
5. Bias and temperature-dependent noise modeling of microwave and millimeter-wave field-effect transistors. [D] . Lardizabal, Steven Marc. 1997

机译：微波和毫米波场效应晶体管的偏置和温度相关噪声建模。
6. Thermal Damage-Free Microwave Annealing with Efficient Energy Conversion for Fabricating of High-Performance a-IGZO Thin-Film Transistors on Flexible Substrates [O] . Ki-Woong Park, Won-Ju Cho 2021

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7. Propriétés électriques et modélisation des dispositifs MOS avanvés : dispositif FD-SOI, transistors sans jonctions (JLT) et transistor à couche mince à semi-conducteur d'oxyde amorphe. Electrical properties and modeling of advanced MOS devices : FD-SOI device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor [O] . Park So Jeong 2013

机译：支持和解释mOsavanvés：dispositif FD-sOI，transistor sans jonctions（JLT）ettransistoràcoucheminceàlele-conducteur d'oxyde amorphe。高级mOs器件的电气特性和建模：FD-sOI器件，无结晶体管和非晶氧化物半导体薄膜晶体管
8. Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance. [R] . Nochetto, H. C., Jankowski, N. R., Morgan, B., 2012

机译：结合GaN衬底热边界电阻的氮化镓（GaN）高电子迁移率晶体管（HEmT）器件的混合多栅模型。

Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

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