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High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels

机译:具有双通道的高性能分栅增强型UMOSFET

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摘要

This paper presents an optimized split-gateenhanced trench MOSFET with dual channels (DSGEUMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance (RON-sp) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot.
机译:本文提出了一种具有双通道的优化的分离栅增强型沟槽MOSFET(DSGEUMOS)。二维设备模拟器ATLAS用于研究所提出结构的特性。与常规SGE-UMOS相比,经过优化的器件在击穿电压为120 V时显示出比导通电阻(RON-sp)明显降低,这是由于采用了额外的p型阱区域所致。此外,提出的结构还可以增强单事件倦怠(SEB)的生存能力。基于DSGE-UMOS,还研究了硬化的DSGE-UMOS(在外延层和衬底层之间添加了n型缓冲层),发现添加缓冲层可以大大提高SEB性能。

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