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首页> 外文期刊>Electron Devices, IEEE Transactions on >Finite-Element Modeling of Retention in Nanocrystal Flash Memories With High- $k$ Interpoly Dielectric Stack
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Finite-Element Modeling of Retention in Nanocrystal Flash Memories With High- $k$ Interpoly Dielectric Stack

机译：高$ k $互电介质堆叠的纳米晶体闪存中保持力的有限元建模

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摘要

The analysis of retention characteristics is essential for reliability assessment of any type of flash memory. A high-k (HK) material in the Interpoly dielectric (IPD) stack is known to improve the program-erase characteristics and makes the control oxide thicker for better retention time; however, it also brings-in defects along with it, creating undesirable charge loss path that plays a significant role in retention. Accurate modeling of this leakage process is important for optimizing the architecture that is less prone to oxide defects and exhibiting improved charge retention. In this paper, we present a physical model considering all possible charge leakage mechanisms that include inelastic tunneling through multiple traps in addition to direct tunneling (DT). The trap capture process is modeled as an inelastic process from nanocrystal (NC) to trap state, while the trap-to-trap tunneling is calculated by Bardeen's Transfer Hamiltonian approach. The trap emission process and DT from the spherical NC are modeled by computing the lifetime of quasi-bound states with very small decay widths in the finite-element setup. We show that a single trap model in HK cannot explain the retention characteristics. We propose a new asymmetric IPD structure that show significant improvement in retention time.
机译：保留特性的分析对于评估任何类型的闪存的可靠性至关重要。众所周知，Interpoly电介质（IPD）叠层中的高k（HK）材料可改善编程擦除特性，并使控制氧化物更厚，从而获得更好的保留时间。然而，它也带来了缺陷，产生了不良的电荷损耗路径，在保留方面起着重要作用。此泄漏过程的准确建模对于优化不易产生氧化物缺陷并改善电荷保持力的架构至关重要。在本文中，我们提出了一种物理模型，其中考虑了所有可能的电荷泄漏机制，这些机制包括除直接隧穿（DT）外还通过多个陷阱的非弹性隧穿。陷阱捕获过程被建模为从纳米晶体（NC）到陷阱状态的非弹性过程，而陷阱到陷阱的隧穿是通过Bardeen的转移哈密顿量法计算的。球形NC的陷阱发射过程和DT是通过计算有限元设置中具有非常小的衰减宽度的准束缚状态的寿命来建模的。我们表明，香港的单一陷阱模型无法解释保留特征。我们提出了一种新的非对称IPD结构，该结构在保留时间上有显着改善。

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