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首页> 外文期刊>IEEE Transactions on Electron Devices >A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment
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A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

机译：深亚微米nMOSFET中铟注入引起的损伤的综合研究：器件表征和损伤评估

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摘要

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.
机译：详细研究了铟沟道注入对深亚微米nMOSFET的电流-电压特性，栅极氧化物击穿和热载流子可靠性的影响。在植入剂量范围为1-2 / spl次/ 10 / sup 13 / cm / sup -2的器件中，观察到在加速电压测试期间氧化物磨损明显加快，并且在热载流子应力期间明显增强了漏极电流的降解。 /。在长通道MOSFET中也测量了重要的发电泄漏，尽管由于主要的亚阈值电流，在短通道器件中通常不会检测到这种不规则性。当植入剂量超过10 / sup 13 / cm / sup -2 /时，装置可靠性的损失可归因于通道中局部非晶区域的产生。后续栅极氧化步骤的有限热预算通常无法消除这些缺陷，从而导致在栅极氧化层中形成局部薄弱点和应变的Si-H键，并在沟道区形成位错环。这一发现引起人们对铟植入在逆行通道工程中的使用的重要关注，因为通常需要有效抑制短通道效应的剂量为10 / sup 13 / cm / sup -2 /数量级。为了最小化器件可靠性的损失，在栅氧化之前将需要使用专用的热退火循环来恢复损坏的晶格。还提出了热载流子应力数据与直流电流电压（DCIV）测量数据之间的良好相关性。通过直接测量过程残留界面陷阱，DCIV技术成为用于深亚微米MOSFET中植入引起的损伤的精确，无损监测器。

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