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Chip diet tests Cisco's resolve

机译:芯片饮食测试思科的决心

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San Jose, Calif.―As the telecom winter drags on, Cisco Systems Inc.'s plan to cut costs by simplifying its diet of electronic components is proving more challenging than expected. Nonetheless, Cisco's top executives have set a course―albeit a wide and somewhat uncertain one―for some of the company's core DRAM, SRAM and microprocessor needs. A new memory council made up of senior engineering and procurement managers axed, at least for the short term, plans to adopt a network-specific DRAM Cisco's engineers had defined, embracing existing fast-cycle and reduced-latency DRAMs instead. The company is, however, working with multiple suppliers on a new SRAM design that would surpass the quad-data-rate SRAMs now coming to market in both speed and density. A similar microprocessor council has agreed to generally standardize around ASICs for data plane processing and the X86 for applications processing. But in the control plane, where Cisco spends 85 percent of its merchant microprocessor budget, the outlook is fuzzy.
机译:随着电信冬季的临近,思科系统公司通过简化其电子元件结构来削减成本的计划被证明比预期更具挑战性。尽管如此,思科的高级管理人员已经为公司的一些核心DRAM,SRAM和微处理器需求设定了一个路线-尽管范围很广而且有些不确定。由高级工程和采购经理组成的一个新的内存理事会至少在短期内已经废除,计划采用思科工程师已定义的特定于网络的DRAM,取而代之的是采用现有的快速周期和降低延迟的DRAM。但是,该公司正在与多家供应商合作开发一种新的SRAM设计,该设计在速度和密度上都将超过目前投放市场的四数据速率SRAM。类似的微处理器理事会已同意总体上围绕用于数据平面处理的ASIC和用于应用程序处理的X86进行标准化。但是在控制层面上,思科花费了其商用微处理器预算的85%,前景是模糊的。

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