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SystemVerilog and ALF standards move forward

机译：SystemVerilog和ALF标准向前发展

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Santa Cruz, Calif. ― EDA standards efforts eased on several fronts last week, as Cadence Design Systems Inc. said it will support Accellera's SystemVerilog language, and Accellera announced IEEE approval of its Advanced Library Format (ALF). Meanwhile, Victor Berman―a respected, 20-year veteran of language standardization efforts―has returned to an active role in which he'll try to resolve current disputes over the future of Verilog. Cadence last week announced that it will support "aspects" of SystemVerilog, but not necessarily Accellera's current SystemVerilog 3.1 specification, which Cadence apparently regards as incomplete. That company also announced the appointment of Berman to the newly created position of group director for Cadence's language and standardization strategy. Separately, Accellera announced that the IEEE has approved ALF, which provides a standard language and semantic representation for design libraries, as IEEE 1603-2003. Additionally, the IEEE approved a new VHDL synthesis subset standard, along with the addition of new features to VHDL.
机译：加利福尼亚州圣克鲁斯市-上周，由于Cadence Design Systems Inc.表示将支持Accellera的SystemVerilog语言，并且Accellera宣布IEEE批准其高级库格式（ALF），EDA标准工作有所缓解。同时，Victor Berman是一位在语言标准化工作上享有20年历史的资深人士，他已重新担任积极角色，他将尝试解决有关Verilog未来的当前争议。 Cadence上周宣布将支持SystemVerilog的“方面”，但不一定支持Accellera当前的SystemVerilog 3.1规范，Cadence显然认为该规范不完整。该公司还宣布任命Berman为Cadence语言和标准化策略的新组长。另外，Accellera宣布IEEE已批准ALF，它为设计库提供了标准语言和语义表示，即IEEE 1603-2003。此外，IEEE批准了新的VHDL合成子集标准，并为VHDL添加了新功能。

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