San Mateo, Calif. ― MIPS Technologies Inc. will wield a new competitive weapon in the embedded-processor wars this week, when it introduces hardware multithreading as an optional extension to its 32-bit and 64-bit architectures. The MIPS announcement will cover architectural definition only―no actual CPU cores using the technology are likely until next year. But by bringing a leading-edge concept from the server world to system-on-chip design, MIPS has suddenly made multithreading a talking point in cores for embedded applications. The company will describe the multi-thread application-specific extension (MT-ASE), as it is known in MIPS parlance, at the Microprocessor Forum, which begins today in San Jose, Calif. MT-ASE is conceptually similar to the hardware multithreading support offered by IBM Corp.'s Power-5 architecture or Intel Corp.'s Pentium Hyper-threading. Additions to the architecture permit the CPU to maintain several separate program threads in cache at the same time and to switch from one thread to another within at most a few clock cycles. A hardware scheduler determines which thread will be accessed for each instruction issue slot.
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