Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references

Mattia O.E.; Klimach H.; Bampi S.

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Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references

机译：CMOS带隙基准电压源的无电阻BJT偏置和曲率补偿电路（3.4nW）

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A novel resistorless bipolar junction transistor (BJT) bias and curvature compensation circuit for ultra-low-power CMOS bandgap voltage references (BGRs) is introduced. It works in the nanoampere current consumption range and under 1 V of power supply. The analytical behaviour of the circuit is described and simulation results for a 0.18 ;C;m CMOS standard process are analysed. A junction voltage of 550 mV at room temperature is obtained (at an emitter current of 3.5 nA), presenting an almost linear temperature dependence, whereas the power consumption of the whole circuit is 3.4 nW under a 0.8 V power supply at 27 0;C. The estimated silicon area is 0.00135 mm2.

机译：介绍了一种新颖的无电阻双极结型晶体管（BJT）偏置和曲率补偿电路，用于超低功耗CMOS带隙基准电压源（BGR）。它工作在纳安电流消耗范围内，并且电源电压低于1V。描述了该电路的分析行为，并分析了0.18; C; m CMOS标准工艺的仿真结果。在室温下获得550 mV的结电压（在3.5 nA的发射极电流下），呈现出几乎线性的温度依赖性，而在27 0; C的0.8 V电源下，整个电路的功耗为3.4 nW。。估计的硅面积为0.00135 mm2。

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《Electronics Letters》 |2014年第12期|863-864|共2页
作者
Mattia O.E.; Klimach H.; Bampi S.;
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PGMICRO ?? Graduate Program on Microelectronics, Informatics Institute, Federal University of Rio Grande do Sul., Porto Alegre, RS, Brazil|c|;

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机译：使用分段曲率温度补偿技术从无电阻CMOS带隙基准电路产生低于1V的基准电压
2. 0.75 V supply nanowatt resistorless sub-bandgap curvature-compensated CMOS voltage reference [J] . Gomez Caicedo Jhon Alexander, Mattia Oscar E., Klimach Hamilton, Analog Integrated Circuits and Signal Processing . 2016,第2期

机译：0.75 V电源纳瓦级无电阻子带隙曲率补偿CMOS电压基准
3. A 139 nW, 67 ppm/degrees C BJT-CMOS-Based Voltage Reference Circuit [J] . Chouhan Shailesh Singh, Halonen Kari Circuits, systems, and signal processing . 2017,第12期

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4. 0.9 V, 5 nW, 9 ppm/^oC resistorless sub-bandgap voltage reference in 0.18#x03BC;m CMOS [C] . Mattia Oscar E., Klimach Hamilton, Bampi Sergio IEEE Latin American Symposium on Circuits and Systems . 2014

机译：0.18μmCMOS中的0.9 V，5 nW，9 ppm / ^{o C无电阻器子带隙基准电压源}
5. Bandgap voltage reference circuits in partially depleted silicon-on-insulator CMOS technology [D] . Wong, Wai-Tat. 2000

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6. Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel [O] . Arthur Spivak, Adam Teman, Alexander Belenky, 2012

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Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references

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