Clock buffer with supply noise active compensation for reduced period jitter

L. Ravezzi

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Clock buffer with supply noise active compensation for reduced period jitter

机译：具有电源噪声有源补偿的时钟缓冲器，可减少周期抖动

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A simple circuit that actively compensates supply noise and reduces period jitter in CMOS clock buffers is presented. The locally sensed supply noise modulates a current injected in the buffer output node during transitions. By injecting the current in opposite phase to the supply noise, the transient variations are counterbalanced and the jitter removed. Designed in a 28 nm CMOS technology, a chain of 16 inverters using the proposed circuit shows a period jitter up to three times smaller than that of an equally long chain of basic inverters. Conventional local supply noise filtering would require approximately 70 times the area used by the proposed circuit to achieve similar performance.

机译：提出了一种简单的电路，该电路可以主动补偿电源噪声并减少CMOS时钟缓冲器中的周期抖动。本地感测到的电源噪声会在过渡期间调制注入缓冲输出节点的电流。通过注入与电源噪声相反相位的电流，可以抵消瞬态变化并消除抖动。采用28 nm CMOS技术进行设计，使用建议的电路的16个反相器链显示的周期抖动比相同长度的基本反相器链的周期抖动小三倍。传统的本地电源噪声滤波将需要大约70倍于拟议电路使用的面积才能实现类似的性能。

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来源
《Electronics Letters》 |2013年第18期|1130-1131|共2页
作者
L. Ravezzi;
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Veloce Technologies, 215 Moffett Park Drive, Sunnyvale, CA 94089, USA;

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正文语种 eng
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专利

1. Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees [J] . Jang J., Franza O., Burleson W. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2012,第1期

机译：全局二进制时钟树的电源噪声引起的周期抖动的紧凑表达式
2. A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation [J] . Mansuri M., Yang C.-K.K. IEEE Journal of Solid-State Circuits . 2003,第11期

机译：具有电源噪声补偿的低功耗自适应带宽PLL和时钟缓冲器
3. A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation [J] . Mozhgan Mansuri, Chih-Kong Ken Yang IEEE Journal of Solid-State Circuits . 2003,第11期

机译：具有电源噪声补偿的低功耗自适应带宽PLL和时钟缓冲器
4. A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter [C] . Jing Li, Jian Luo, Yongfeng Ding, IEEE Asia Pacific Conference on Circuits and Systems . 2018

机译：用于时钟缓冲器的电源噪声补偿电路，以减少时序抖动
5. Low-jitter PLL for clock generator with supply-noise-insensitive VCO using DC-DC capacitive converter. [D] . Lee, Chang-Hyeon. 1999

机译：用于时钟发生器的低抖动PLL，具有使用DC-DC电容转换器的对电源噪声不敏感的VCO。
6. period-1 encodes an ATP-dependent RNA helicase that influences nutritional compensation of the Neurospora circadian clock [O] . Jillian M. Emerson, Bradley M. Bartholomai, Carol S. Ringelberg, 2015

机译：period-1编码影响神经孢子生物钟时钟营养补偿的ATP依赖性RNA解旋酶
7. The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter [O] . Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, 2013

机译：工艺变化和电源噪声对时钟偏移和抖动的综合影响

Clock buffer with supply noise active compensation for reduced period jitter

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