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Maximum-likelihood based lock detectors for M-PSK carrier phase tracking loops

机译:用于M-PSK载波​​相位跟踪环路的基于最大似然性的锁定检测器

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摘要

Carrier phase synchronisation is essential for coherent communications. Receivers typically use digital phase-locked loops (DPLLs) to acquire the carrier phase. The lock range of DPLLs, i.e. the range of frequency offsets that they can acquire, is usually significantly less than the initial frequency uncertainty in typical systems. Hence, acquisition is achieved by sweeping through the frequency uncertainty range, and stopping the sweep when the DPLL acquires the signal. Since the transmitted data symbols are in general unknown, successful acquisition is determined by a non-data aided carrier lock detector (CLD). In this reported work, a maximum-likelihood based CLD is derived which has low implementation complexity, and is better than existing CLDs while being impervious to errors in the receive Automatic Gain Control (AGC).
机译:载波相位同步对于相干通信至关重要。接收器通常使用数字锁相环(DPLL)来获取载波相位。 DPLL的锁定范围,即它们可以获取的频率偏移范围,通常明显小于典型系统中的初始频率不确定度。因此,通过扫过频率不确定性范围并在DPLL采集信号时停止扫频来实现采集。由于通常不知道所发送的数据符号,因此由非数据辅助的载波锁定检测器(CLD)确定成功的捕获。在此报告的工作中,得出了基于最大似然的CLD,它具有较低的实现复杂度,并且比现有的CLD更好,同时不受接收自动增益控制(AGC)中的错误的影响。

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  • 来源
    《Electronics Letters》 |2012年第4期|p.242-244|共3页
  • 作者

    Ramakrishnan B.;

  • 作者单位

    The MITRE Corporation, MA, USA;

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  • 原文格式 PDF
  • 正文语种 eng
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