Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

Sanchez-Renedo M.; Paton S.

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Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

机译：级间网络可控制级联连续时间/ spl Sigma // spl Delta /调制器中的过载

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摘要

An improved interstage network suitable for avoiding overload and for increasing the signal-to-noise ratio in low-oversampling-ratio cascaded continuous-time SigmaDelta modulators is reported. Feedforward coefficients, going from the input signal to the second stage, are used to control overload without affecting the behaviour of the noise cancellation filters. Moreover, the anti-aliasing functionality is preserved. Simulation results show the utility of the proposed network in terms of the overload performance

机译：报道了一种改进的级间网络，适用于避免过载和增加低过采样率级联连续时间SigmaDelta调制器中的信噪比。从输入信号到第二级的前馈系数用于控制过载，而不会影响噪声消除滤波器的性能。此外，保留了抗锯齿功能。仿真结果表明了所提网络在过载性能方面的实用性。

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来源
《Electronics Letters》 |2007年第12期|p.664-665|共2页
作者
Sanchez-Renedo M.; Paton S.;
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正文语种 eng
中图分类无线电电子学、电信技术;
关键词
continuous time systems; interference suppression; modulators; sigma-delta modulation; cascaded continuous-time SigmaDelta modulators; feedforward coefficients; interstage network; noise cancellation filters; overload control; signal-to-noise ratio;

机译：连续时间系统;干扰抑制;调制器;sigma-delta调制;级联连续时间SigmaDelta调制器;前馈系数;级间网络;降噪滤波器;过载控制;信噪比;

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专利

1. A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology [J] . Medeiro F., Perez-Verdu B. IEEE Journal of Solid-State Circuits . 1999,第6期

机译：CMOS 0.7- / spl mu / m单晶技术中的13位，2.2-MS / s，55mW多位级联/ spl Sigma // spl Delta /调制器
2. Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays [J] . Sobot R., Stapleton S., Syrzycki M. IEEE Transactions on Circuits and Systems. I, Regular Papers . 2006,第2期

机译：可调谐的连续时间带通/ spl Sigma // spl Delta /调制器，具有分数延迟
3. A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth [J] . Caldwell T.C., Johns D.A. IEEE Journal of Solid-State Circuits . 2006,第7期

机译：具有20 MHz信号带宽的时间交错的连续时间/ spl Delta // spl Sigma /调制器
4. Design of a 1.2-V cascade continuous-time /spl Delta//spl Sigma/ modulator for broadband telecommunications [C] . Tortosa R., de la Rosa J.M., Rodriguez-Vazquez A., IEEE International Symposium on Circuits and Systems . 2006

机译：1.2V级联连续时间/ SPL DELTA // SPL SIGMA /调制器的设计为宽带电信
5. Design techniques for ultralow voltage CMOS continuous-time filters and continuous-time sigma-delta modulators. [D] . Huang, Huanzhang. 2001

机译：超低压CMOS连续时间滤波器和连续时间sigma-delta调制器的设计技术。
6. The microRNA regulated SBP-box genes SPL9 and SPL15 control shoot maturation in Arabidopsis [O] . Stefan Schwarz, Arne V. Grande, Nora Bujdoso, -1

机译：microRNA调控的SBP-box基因SPL9和SPL15控制拟南芥的茎成熟
7. Systematic design of high-resolution high-frequency cascade continuous-time sigma-delta modulators [O] . Tortosa, Ramón, Castro-López, R., Rosa, José M. de la, 2013

机译：高分辨率高频级联连续时间sigma-delta调制器的系统设计

Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

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