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首页> 外文期刊>Embedded Systems Letters, IEEE >Synthesis of Parallel Synchronous Software
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Synthesis of Parallel Synchronous Software

机译：并行同步软件的合成

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摘要

In typical embedded applications, the precise execution time of the program does not matter and it is sufficient to meet a real-time deadline. However, modern applications in information security have become much more time-sensitive due to the risk of timing side-channel leakage. The timing of such programs needs to be data-independent and precise. We describe a parallel synchronous software model, which executes as N parallel threads on a processor with word-length N . Each thread is a single-bit synchronous machine with precise, contention-free timing, while each of the N threads still executes as an independent machine. The resulting software supports fine-grained parallel execution. In contrast to earlier work to obtain precise and repeatable timing in software, our solution does not require modifications to the processor architecture nor specialized instruction scheduling techniques. In addition, all threads run in parallel and without contention, which eliminates the problem of thread scheduling. We use hardware (HDL) semantics to describe a thread as a single-bit synchronous machine. Using logic synthesis and code generation, we derive a parallel synchronous implementation of this design. We illustrate the synchronous parallel programming model with practical examples from cryptography and other applications with precise timing requirements.
机译：在典型的嵌入式应用程序中，程序的精确执行时间无关紧要，满足实时截止日期就足够了。然而，由于定时侧通道泄漏的风险，信息安全中的现代应用变得更加敏感。这些程序的时间需要与数据无关和精确。我们描述了一个并行同步软件模型，它在具有字长N的处理器上执行AS N并行线程。每个线程都是单位同步机，具有精确，争用的定时，而N个线程中的每一个仍然被执行为独立机器。生成的软件支持细粒度并行执行。与早期的工作相比，在软件中获得精确和可重复的时机，我们的解决方案不需要修改处理器架构，也不需要修改，也不需要专门的指令调度技术。此外，所有线程都在并行运行且不争用，从而消除了线程调度的问题。我们使用硬件（HDL）语义来描述一个单位作为单位同步机的线程。使用逻辑综合和代码生成，我们推出了这种设计的并行同步实现。我们说明了具有来自加密和其他应用的实际示例的同步并行编程模型，具有精确的定时要求。

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