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首页> 外文期刊>Emerging and Selected Topics in Circuits and Systems, IEEE Journal on >Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters
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Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters

机译：通过在紧密耦合的处理器群集中向软件暴露可变性影响，提高对时序错误的适应性

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摘要

Manufacturing and environmental variations cause timing errors in microelectronic processors that are typically avoided by ultra-conservative multi-corner design margins or corrected by error detection and recovery mechanisms at the circuit-level. In contrast, we present here runtime software support for cost-effective countermeasures against hardware timing failures during system operation. We propose a variability-aware OpenMP (VOMP) programming environment, suitable for tightly-coupled shared memory processor clusters, that relies upon modeling across the hardware/software interface. VOMP is implemented as an extension to the OpenMP v3.0 programming model that covers various parallel constructs, including ${tt task}$, ${tt sections}$, and ${tt for}$. Using the notion of work-unit vulnerability (WUV) proposed here, we capture timing errors caused by circuit-level variability as high-level software knowledge. WUV consists of descriptive metadata to characterize the impact of variability on different work-unit types running on various cores. As such, WUV provides a useful abstraction of hardware variability to efficiently allocate a given work-unit to a suitable core for execution. VOMP enables hardware/software collaboration with online variability monitors in hardware and runtime scheduling in software. The hardware provides online per-core characterization of WUV metadata. This metadata is made available by carefully placing key data structures in a shared L1 memory and is used by VOMP schedulerss. Our results show that VOMP greatly reduces the cost of timing error recovery compared to the baseline schedulers of OpenMP, yielding speedup of 3%–36% for tasks, and 26%–49% for sections. Further, VOMP reaches energy saving of 2%–46%- and 15%–50% for tasks, and sections, respectively.
机译：制造和环境变化会引起微电子处理器中的时序错误，通常可以通过超保守的多角设计余量来避免这种时序错误，或者通过电路级的错误检测和恢复机制来纠正这种错误。相比之下，我们在此提供运行时软件支持，以针对系统运行期间的硬件计时故障提供经济有效的对策。我们提出了一个可变性感知的OpenMP（VOMP）编程环境，该环境适用于紧密耦合的共享内存处理器集群，它依赖于跨硬件/软件接口的建模。 VOMP被实现为OpenMP v3.0编程模型的扩展，该模型涵盖了各种并行构造，包括$ {tt task} $，$ {tt section} $和$ {tt for} $。使用此处提出的工作单元漏洞（WUV）的概念，我们可以将电路级可变性引起的时序错误捕获为高级软件知识。 WUV由描述性元数据组成，以描述可变性对在各种内核上运行的不同工作单元类型的影响。这样，WUV提供了有用的硬件可变性抽象，可以有效地将给定的工作单元分配给合适的内核以执行。 VOMP可以与硬件中的在线可变性监视器进行硬件/软件协作，并与软件中的运行时调度实现协作。该硬件提供WUV元数据的在线每核特征。通过将关键数据结构小心地放置在共享的L1内存中，可以使该元数据可用，并且由VOMP调度程序使用。我们的结果表明，与OpenMP的基线计划程序相比，VOMP大大降低了定时错误恢复的成本，任务的处理速度提高了3％–36％，节的处理速度提高了26％–49％。此外，VOMP分别为任务和部门节省了2％–46％-和15％–50％的能源。

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