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A low-power analog correlation processor for real-time camera alignment and motion computation

机译:低功耗模拟相关处理器,用于实时摄像机对准和运动计算

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A design is presented for a low-power switched-current block correlation processor, which produces a set of feature matches between pairs of binary edge images. The novelty and usefulness of the processor stem from the reliability of its outputs. Statistical tests are included to minimize the probability that the correspondences found have occurred by chance. The results may be used without further refinement to accurately compute the epipolar geometry between two camera positions. The primary applications of this processor are computing camera motion and providing coarse alignment of two images acquired from similar sensors. An analog design was chosen to reduce circuit area in order to accommodate both large template blocks and search areas. Switched current sources at each pixel are summed on a single wire, while analog comparators implement the validation tests and track the minimum score. A prototype 5/spl times/5 block processor with a 9/spl times/9 search area was fabricated as a "Tiny Chip" through MOSIS in a 1.2-/spl mu/m complimentary metal-oxide-semiconductor (CMOS) process. The chip correctly determined the correct matches for the given patterns and dissipated no more than 12 /spl mu/W of static power per pixel in continuous operation. In a full-scale implementation, an array of several large (e.g., 24/spl times/24) block processors could be placed single 1 cm/sup 2/ die. Measurements indicate that the computations for each block offset can be processed in less than 200 ns, implying that a 200/spl times/200 area can be searched in 8 ms.
机译:提出了一种针对低功率开关电流块相关处理器的设计,该处理器在成对的二进制边缘图像之间产生一组特征匹配。处理器的新颖性和实用性源于其输出的可靠性。包括统计测试,以使找到的对应关系偶然发生的可能性降到最低。无需进一步优化即可使用结果,以准确计算两个相机位置之间的对极几何形状。该处理器的主要应用是计算摄像机运动并提供从相似传感器获取的两个图像的粗对准。选择了一种模拟设计以减少电路面积,以便同时容纳较大的模板块和搜索区域。每个像素处的开关电流源都通过单线求和,而模拟比较器执行验证测试并跟踪最小分数。通过MOSIS以1.2- / spl mu / m互补金属氧化物半导体(CMOS)工艺将具有9 / spl times / 9搜索区域的5 / spl times / 5块原型处理器制作为“微型芯片”。该芯片正确地确定了给定模式的正确匹配,并且在连续操作中每个像素耗散的静态功率不超过12 / spl mu / W。在全面实施中,几个大型(例如24 / spl次/ 24)块处理器的阵列可以放置在单个1cm / sup 2 /管芯上。测量表明,每个块偏移的计算可以在不到200 ns的时间内处理,这意味着可以在8 ms内搜索200 / spl次/ 200区域。

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