Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

Mazumder P.

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Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

机译：布局优化以提高片上VLSI / WSI并行处理的良率

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The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-efficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application to mapping a variety of processor geometries onto specific array networks. The layout algorithms are expressed in a new notational language, which is amenable to cellular layout in contrast to classical procedural languages. The layout technique is illustrated with both well known parallel-processing array networks and a new fault-tolerant square mesh with reconfigurable processors and interconnect. The square mesh with redundant processors provides high yield and operational reliability.

机译：本文研究了处理器阵列网络的布局优化问题。如果为处理器选择了合适的形状几何形状，则可以在VLSI / WSI芯片上将特定的互连网络有效地映射到区域上，以最大程度地提高芯片产量，操作可靠性和电路性能。提出了一种通过多米诺砖块进行蜂窝布局的形式化技术，并将其应用于将各种处理器几何形状映射到特定阵列网络上。布局算法以一种新的记法语言表示，与经典的过程语言相比，它适合于蜂窝布局。通过众所周知的并行处理阵列网络和具有可重配置处理器和互连功能的新型容错方形网格，说明了布局技术。带冗余处理器的方形网格可提供高产量和操作可靠性。

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《IEE Proceedings. Part E》 |1992年第1期|P.21-28|共8页
作者
Mazumder P.;
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正文语种 eng
中图分类计算技术、计算机技术;
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Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

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