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首页> 外文期刊>IEEE Transactions on Circuits and Systems. II >C-configurability and built-in-test of reconfigurable processor array interconnection networks
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C-configurability and built-in-test of reconfigurable processor array interconnection networks

机译：可重配置处理器阵列互连网络的C可配置性和内置测试

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摘要

A general-purpose interconnection switch applicable to reconfigurable architectures is described. The switch has been used in the design of reconfigurable architectures and in processor arrays that require reconfigurable interconnections. The reconfigurable switch has the desirable properties that it is both scalable and C-testable. Furthermore, the switch is shown to be C-configurable: that is, the number of configurations required to test a network of switches is independent of the size of the network. Criteria are given for selecting built-in-test (BIT) techniques and implementations for reconfigurable architectures. Algorithms for generating configuration values and test data are presented. The BIT implementation is presented and analyzed and is shown to provide 100% fault coverage for single S-A-0, S-A-1, bridging, and high-impedance, permanent combinational faults.
机译：描述了适用于可重构体系结构的通用互连交换机。该交换机已用于可重配置体系结构的设计和需要可重配置互连的处理器阵列中。可重新配置的交换机具有可伸缩和C测试的理想特性。此外，交换机显示为可C配置的：也就是说，测试交换机网络所需的配置数量与网络的大小无关。给出了为可重配置架构选择内置测试（BIT）技术和实现的标准。给出了用于生成配置值和测试数据的算法。展示并分析了BIT的实现方式，并显示出该功能可为单个S-A-0，S-A-1，桥接和高阻抗永久性组合故障提供100％的故障覆盖率。

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