A SDH STM-N Processor for Overhead Terminating and PDH Interface

Shi Fuqiang; Wang Yilun; Lin Xiaokang

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A SDH STM-N Processor for Overhead Terminating and PDH Interface

机译：用于开销终止和PDH接口的SDH STM-N处理器

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A single-chip Synchronous Digital Hierarchy STM-N processor has been developed. The cell based chip has been fabricated in a 0.5 μm CMOS process. It contains 280k gatesand 240 pins. The chip can be configured in several operation modes: STM-N overhead termina- tor, E4 )139.264Mb/s) mapper, ADM(Add/Drop Multiplex) E1 (2.048 Mb/s) mapper, 150 Mb/s ATM interface and 2 Mb/s ATM interface. This paper describes the architecture of the IC, and the chip's several interesting features.

机译：已经开发出单芯片同步数字体系STM-N处理器。基于单元的芯片已采用0.5μmCMOS工艺制造。它包含28万个门和240个引脚。该芯片可以配置为几种工作模式：STM-N开销终端，E4 139.264Mb / s映射器，ADM（Add / Drop Multiplex）E1（2.048 Mb / s）映射器，150 Mb / s ATM接口和2 Mb / s ATM接口。本文介绍了IC的体系结构以及该芯片的一些有趣功能。

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来源
《High Technology Letters》 |1999年第1期|p.25-28|共4页
作者
Shi Fuqiang; Wang Yilun; Lin Xiaokang;
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原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
SDH/SONET; ASIC; ADM (Add/Drop Multiplex);

机译：SDH / SONET;ASIC;ADM（加/减复用）;

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1. A SDH STM-N Processor for Overhead Terminating and PDH Interface [J] . 史富强高技术通讯：英文版 . 1999,第001期

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2. A SONET/SDH overhead terminator for STS-3, STS-3C, and STM-1 [J] . Hamlin R.W. Jr., Parruck B. IEEE Journal of Solid-State Circuits . 1993,第3期

机译：用于STS-3，STS-3C和STM-1的SONET / SDH开销终结器
3. Optimisation and performance assessment of a digital signal-processing method for jitter measurement in PDH/SDH-based digital telecommunication networks [J] . Leopoldo Angrisani Measurement . 2003,第4期

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4. Phase deviations on SDH and SDH/PDH interface [C] . Nowosad, P., Kuh, . 1993

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A SDH STM-N Processor for Overhead Terminating and PDH Interface

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