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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Threshold Voltage Mismatch and Intra-Die Leakage Current in Digital CMOS Circuits
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Threshold Voltage Mismatch and Intra-Die Leakage Current in Digital CMOS Circuits

机译：数字CMOS电路中的阈值电压不匹配和芯片内漏电流

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摘要

Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I{sub}(off)) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (△V{sub}(to)) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V{sub}t mismatch shift. This effect can be so severe that J{sub}(off) can increase by more than one order of magnitude with respect to its nominal value due only to V{sub}(to) mismatch. We further show through experimental results that the V{sub}(to) mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I{sub}(off) level as for a V{sub}(to) mismatch characterized out of the subthreshold regime.
机译：由于当前和将来的深亚微米CMOS技术的器件和电压缩放方案，不可避免地随着技术最小尺寸的缩小，MOSFET晶体管的截止状态电流（I {sub}（off））会增加。实验证据表明，现代深亚微米设计的泄漏电流分布不仅具有较高的平均值，而且还具有较大的可变性。在本文中，我们调查了阈值电压不匹配的影响，认为这是这种可变性增加的一个合理来源。在数字电路设计中，通常假定静态CMOS单元的阈值电压差（失配）可忽略不计。但是，阈值电压不匹配（△V {sub}（to））对截止状态电流具有双向影响。即，总电池的电流可以根据V {t}失配偏移的方向而增加或减少。这种影响可能非常严重，以至于J {sub}（off）只能由于V {sub}（to）不匹配而相对其标称值增加一个数量级以上。通过实验结果，我们进一步表明，与在饱和或线性区域中工作的晶体管相比，在低于阈值状态下工作的成对晶体管的V {sub}（to）不匹配可能会恶化两倍。如果希望获得与表征的V {sub}（to）不匹配相同的I {sub}（off）电平，则在面积，速度和功耗方面，两个较大的扩展系数显然会毁灭性很大。亚阈值制度。

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