• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE transactions on biomedical circuits and systems >MorphIC: A 65-nm 738k-Synapse/mm
【24h】

MorphIC: A 65-nm 738k-Synapse/mm

机译：MorphIC：65纳米738k突触/毫米

获取原文
获取原文并翻译 | 示例
       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient SNNs still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this paper, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$2$ in 65-nm CMOS, achieving a high density of 738k synapses/mm$2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.
机译：神经网络加速器领域的最新趋势正在研究权重量化，以增加硬件设备的资源和功率效率。由于必须使用完整的片上权重存储来避免片外存储器访问的高能耗，因此，对于权重存储的内存减少要求已推向二进制权重的使用，事实证明，量化时在许多应用中精度降低有限使用意识训练技术。同时，在处理基于事件的稀疏数据流时，探索了尖峰神经网络（SNN）架构以进一步降低功耗，而基于片上尖峰的在线学习似乎是培训阶段功率和资源受限的应用程序的关键功能。 。然而，设计具有功率和面积效率的SNN仍需要开发特定技术，以便在二进制权重上利用片上在线学习而不损害突触密度。在本文中，我们演示了MorphIC，这是一种四核二进制加权数字神经形态处理器，它嵌入了峰值驱动的突触可塑性（S-SDSP）学习规则的随机版本和用于大规模芯片互连的分层路由结构。 MorphIC SNN处理器在65纳米CMOS中嵌入了总计2k的泄漏集成激发（LIF）神经元和超过200万个塑料突触，从而使有源硅面积为2.86mm 2美元，实现了73.8万突触/的高密度。毫米2美元。与先前提出的SNN相比，MorphIC证明了MNIST分类任务在区域精度折衷方面的数量级改进，而在能量精度折衷方面没有任何损失。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号