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首页> 外文期刊>IEEE transactions on biomedical circuits and systems >A Hardware-Efficient Scalable Spike Sorting Neural Signal Processor Module for Implantable High-Channel-Count Brain Machine Interfaces
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A Hardware-Efficient Scalable Spike Sorting Neural Signal Processor Module for Implantable High-Channel-Count Brain Machine Interfaces

机译：用于植入式高通道数脑机接口的硬件有效的可扩展穗式排序神经信号处理器模块

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摘要

Next-generation brain machine interfaces demand a high-channel-count neural recording system to wirelessly monitor activities of thousands of neurons. A hardware efficient neural signal processor (NSP) is greatly desirable to ease the data bandwidth bottleneck for a fully implantable wireless neural recording system. This paper demonstrates a complete multichannel spike sorting NSP module that incorporates all of the necessary spike detector, feature extractor, and spike classifier blocks. To meet high-channel-count and implantability demands, each block was designed to be highly hardware efficient and scalable while sharing resources efficiently among multiple channels. To process multiple channels in parallel, scalability analysis was performed, and the utilization of each block was optimized according to its input data statistics and the power, area and/or speed of each block. Based on this analysis, a prototype 32-channel spike sorting NSP scalable module was designed and tested on an FPGA using synthesized datasets over a wide range of signal to noise ratios. The design was mapped to 130 nm CMOS to achieve 0.75 μW power and 0.023 mm area consumptions per channel based on post synthesis simulation results, which permits scalability of digital processing to 690 channels on a 4×4 mm electrode array.
机译：下一代脑机接口需要一个高通道数的神经记录系统，以无线方式监视数千个神经元的活动。非常需要硬件有效的神经信号处理器（NSP），以减轻完全可植入的无线神经记录系统的数据带宽瓶颈。本文演示了一个完整的多通道尖峰分类NSP模块，该模块集成了所有必需的尖峰检测器，特征提取器和尖峰分类器模块。为了满足高通道数和可植入性的要求，每个模块的设计都具有很高的硬件效率和可扩展性，同时在多个通道之间有效地共享资源。为了并行处理多个通道，执行了可伸缩性分析，并根据其输入数据统计信息以及每个块的功率，面积和/或速度来优化每个块的利用率。基于此分析，设计了一个原型32通道尖峰排序NSP可扩展模块，并在FPGA上使用合成的数据集在各种信噪比范围内对其进行了测试。根据后期合成仿真结果，该设计被映射到130nm CMOS以实现0.75μW功率和每通道0.023mm的面积消耗，这允许数字处理在4×4mm电极阵列上可扩展至690个通道。

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