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首页> 外文期刊>Biomedical Circuits and Systems, IEEE Transactions on >Variable-Gain, Low-Noise Amplification for Sampling Front Ends
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Variable-Gain, Low-Noise Amplification for Sampling Front Ends

机译：采样前端的可变增益，低噪声放大

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摘要

This paper presents a low-noise front-end amplifier with configurable gain, targeting the recording of small signals, such as the electrocardiogram (ECG) or electroneurogram (ENG). The circuit consists of a continuous-time input stage using lateral bipolar transistors realized in complementary metal–oxide semiconductor (CMOS) technology followed by a switched-capacitor integrating stage. The voltage gain is adjustable by varying the phase delay between two system clocks. Simulated and measured results for a chip fabricated in 0.35-$mu$m CMOS technology are reported. The amplifier occupies an active area of 0.064 mm $^{2}$, yields a nominal gain of 630 V/V with more than a 50-dB tuning range, less than 16 ${rm nV}_{rm rms}/surd{rm Hz}$ input noise and a common-mode rejection of more than 97 dB. Its power consumption is 280 $mu$W with a $pm$1.5-V supply.
机译：本文提出了一种具有可配置增益的低噪声前端放大器，其目标是记录小信号，例如心电图（ECG）或电子神经图（ENG）。该电路包括一个连续时间输入级，该级使用横向双极型晶体管以互补金属氧化物半导体（CMOS）技术实现，其后是一个开关电容器集成级。通过改变两个系统时钟之间的相位延迟，可以调节电压增益。报告了用0.35-μmCMOS技术制造的芯片的仿真和测量结果。该放大器的有效面积为0.064 mm 2，$，产生标称增益630 V / V，调谐范围大于50 dB，小于16rms / rmd {rm Hz} $输入噪声和超过97 dB的共模抑制。电源为pm $ 1.5-V时，其功耗为280μmuW。

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