A 25-Gb/s 270-mW Time-to-Digital Converter-Based<inline-formula><tex-math notation='LaTeX'>$8{imes}$</tex-math></inline-formula>Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

Sami Ur Rehman; Mohammad Mahdi Khafaji; Corrado Carta; Frank Ellinger

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$8{imes}$

Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

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A 25-Gb/s 270-mW Time-to-Digital Converter-Based$8{imes}$Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

机译：基于25 Gb / s 270 mW时间数字转换器的 $ 8 { times} $ 在45nm SOI CMOS中过采样输入延迟的数据接收器

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This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The proposed 64-tapped adaptable-delay-line-based design is intended as a high-rate oversampling baseband binary quantizer for a high-speed serial link. The data-receiver has been demonstrated to digitize up to 25-Gb/s input binary symbol sequences with an oversampling ratio of eight. Designed in a 45-nm SOI CMOS process, the receiver circuit is fully characterized by applying different symbol sequences at its input while setting its time resolution and dynamic-range/delay to 5 and 320 ps, respectively. Under these conditions, the data-receiver consumes 270 mW of power, and achieves an energy conversion figure of 1.62-4.32 pJ/sampled-digital-bit. The circuit occupies 0.24 mm^{2of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far.}

机译：本文提出了一种基于时间数字转换器的过采样输入延迟多标准自适应数据接收器体系结构，该体系结构将时变二进制输入符号序列内的跃迁/阈值穿越和跃迁距离数字化。所提出的电路通过对差分延迟线内的跨阈值二进制输入符号序列的延迟副本进行采样来工作。所得的采样数字字携带阈值交叉及其之间的距离的信息。拟议的基于64抽头的自适应延迟线设计旨在用作高速串行链路的高速率过采样基带二进制量化器。数据接收器已被证明可以以高达8的过采样率数字化高达25 Gb / s的输入二进制符号序列。接收器电路采用45纳米SOI CMOS工艺设计，其特征在于在其输入端应用不同的符号序列，同时将其时间分辨率和动态范围/延迟分别设置为5和320 ps。在这些条件下，数据接收器消耗270 mW的功率，并实现1.62-4.32 pJ /采样数字位的能量转换系数。电路占用0.24 mm n ^{2 n有源硅区域。与迄今报道的过采样时间模式接收机架构相比，拟议中的接收机提供了最高的时间分辨率和过采样因子之一，并且是最佳的能量转换指标之一。}

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来源
《IEEE transactions on circuits and systems . I , Regular papers》 |2018年第11期|3720-3733|共14页
作者
Sami Ur Rehman; Mohammad Mahdi Khafaji; Corrado Carta; Frank Ellinger;
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作者单位

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden, Germany;

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正文语种 eng
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关键词
Receivers; Clocks; Wireless communication; Pulse width modulation; Wideband; Baseband; Hardware;

机译：接收机;时钟;无线通信;脉宽调制;宽带;基带;硬件;

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A 25-Gb/s 270-mW Time-to-Digital Converter-Based$8{imes}$Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

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