WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks

Chen Yang; Yizhou Wang; Xiaoli Wang; Li Geng

首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks

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WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks

机译：WRA：使用新型Winograd分解算法的卷积神经网络的2.2至6.3 TOPS高度统一的动态可重新配置加速器

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As convolutional neural networks (CNNs) become more and more diverse and complicated, acceleration of CNNs increasingly encounters a bottleneck of balancing performance, energy efficiency, and flexibility in a unified architecture. This paper proposed a W

机译：随着卷积神经网络（CNN）变得越来越多样化和复杂，CNN的加速越来越遇到在统一体系结构中平衡性能，能源效率和灵活性的瓶颈。本文提出了一个W

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来源
《Circuits and Systems I: Regular Papers, IEEE Transactions on》 |2019年第9期|3480-3493|共14页
作者
Chen Yang; Yizhou Wang; Xiaoli Wang; Li Geng;
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作者单位

School of Microelectronics Xi’an Jiaotong University Xi’an China;

School of Microelectronics Xi’an Jiaotong Universi;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Convolution; Hardware; Acceleration; Computer architecture; Parallel processing; Throughput; Shape;

机译：卷积;硬件;加速;计算机架构;并行处理;吞吐量;形状;

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专利

1. WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm [J] . Wang Xuan, Wang Chao, Cao Jing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2020,第11期

机译：WINONN：使用稀疏Winograd算法优化基于FPGA的卷积神经网络加速器
2. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks [J] . Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Solid-State Circuits, IEEE Journal of . 2017,第1期

机译：Eyeriss：适用于深度卷积神经网络的节能型可重构加速器
3. 11 TOPS photonic convolutional accelerator for optical neural networks [J] . Xu Xingyuan, Tan Mengxi, Corcoran Bill, Nature . 2021,第7840期

机译：11顶层光学神经网络的光子卷积加速器
4. A reconfigurable accelerator based on fast Winograd algorithm for convolutional neural network in Internet of Things [C] . Chen Yang, YiZhou Wang, XiaoLi Wang, IEEE International Conference on Solid-State and Integrated Circuit Technology . 2018

机译：基于快速Winograd算法的可重构加速器在物联网中的卷积神经网络
5. Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms [D] . Barnes, Robert C. 2009

机译：动态可重构脉动阵列加速器：扩展卡尔曼滤波器和离散小波变换算法的案例研究
6. Sign Language Recognition Using Wearable Electronics: Implementing k-Nearest Neighbors with Dynamic Time Warping and Convolutional Neural Network Algorithms [O] . Giovanni Saggio, Pietro Cavallo, Mariachiara Ricci, 2020

机译：使用可穿戴电子产品的手语识别：实现K-Cirseld邻居具有动态时间翘曲和卷积神经网络算法
7. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks [O] . Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, 2017

机译：Eyeriss：用于深卷积神经网络的节能可重构加速器

WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks

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