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首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >A Class of 1-Bit Multi-Step Look-Ahead Σ - Δ Modulators
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A Class of 1-Bit Multi-Step Look-Ahead Σ - Δ Modulators

机译：一类1位多步超前Σ-Δ调制器

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摘要

Digital Multi-Step Look-Ahead (MSLA) 1-bit Σ-Δ modulators are introduced. They improve upon the stability and noise shaping characteristics of conventional 1-bit Σ-Δ modulators by minimizing quantization error metrics of the current and future output samples. The mathematical model of the proposed MSLA modulators is analyzed. It is shown that the MSLA modulators are equivalent to a system of conventional Σ-Δ modulators in parallel, but with a common multi-input 1-bit quantizer instead of a typical one. The properties of this multi-input quantizer are studied and the transfer functions of the MSLA modulators are derived. Simulation results are presented demonstrating the advantages of the MSLA modulators over conventional 1-bit Σ-Δ ones in a number of applications. A parametric hardware architecture of the MSLA modulators is presented offering an adjustable trade-off between performance and hardware complexity based on the number of look-ahead steps. Finally, a FPGA implementation of a MSLA modulator is presented along with simulation results.
机译：引入了数字多步超前（MSLA）1位Σ-Δ调制器。它们通过最小化当前和未来输出样本的量化误差度量，改善了传统1位Σ-Δ调制器的稳定性和噪声整形特性。分析了所提出的MSLA调制器的数学模型。可以看出，MSLA调制器等效于并行的常规Σ-Δ调制器系统，但是具有通用的多输入1位量化器，而不是典型的量化器。研究了这种多输入量化器的特性，并推导了MSLA调制器的传递函数。给出的仿真结果证明了MSLA调制器在许多应用中优于传统的1位Σ-Δ调制器的优势。提出了MSLA调制器的参数化硬件体系结构，可根据预见步骤的数量在性能和硬件复杂度之间进行可调整的折衷。最后，介绍了MSLA调制器的FPGA实现以及仿真结果。

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