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首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation
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Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation

机译：高效无因数修正余弦梳理抽取滤波器的设计：分析与实现

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This paper presents a computationally efficient design of modified cosine-based decimation filters. One of the main contributions of this paper is the proposal of a multiplierless finite impulse response low-order linear-phase filter to increase spurious signal rejection in the so-called folding bands. The resulting filters feature reduced computational complexity compared with other recent proposals in the literature, as well as higher folding-band attenuation than traditional comb filters. The frequency behavior of the proposed class of decimation filters is compared with generalized comb filters as well as other proposals in the recent literature. Moreover, this paper addresses field-programmable gate array implementation of the proposed filters in a variety of structures, including both nonrecursive and recursive architectures, and it evaluates and compares the performance of these architectures in terms of area and power consumption. A critical comparison is provided with the goal of highlighting key design issues and computational efficient implementations for the interested reader.
机译：本文提出了一种改进的基于余弦的抽取滤波器的高效计算设计。本文的主要贡献之一是提出了一种无乘有限脉冲响应低阶线性相位滤波器，以提高所谓折叠带中的杂散信号抑制能力。与传统的梳状滤波器相比，与文献中的其他最新提议相比，所得的滤波器具有降低的计算复杂度以及折叠带衰减更高的特点。将所提出的一类抽取滤波器的频率特性与广义梳状滤波器以及最新文献中的其他提议进行了比较。此外，本文介绍了所提出的滤波器在各种结构中的现场可编程门阵列实现，包括非递归和递归架构，并就面积和功耗评估和比较了这些架构的性能。提供了关键的比较，目的是为感兴趣的读者突出关键设计问题和有效的计算实现。

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