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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems
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A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

机译：用于神经记录系统的高效节能连续时间增量Sigma-Delta ADC

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摘要

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 , which corresponds to a figure-of-merit of 0.85 pJ/conv.
机译：本文介绍了专用于神经记录系统的模数转换器（ADC）。通过在流水线配置中使用两个连续时间增量式sigma-delta ADC，建议的ADC可以在不牺牲转换速率的情况下实现高分辨率。这种两步式架构还具有高能效，因为大大降低了每一步中增量sigma-delta ADC的分辨率要求。为了进一步提高功率效率，AB类输出级和动态求和比较器用于实现sigma-delta调制器。以标准的0.18 CMOS工艺设计和制造的原型芯片验证了所提议的ADC体系结构。测量结果表明，ADC在4 kHz带宽上实现了75.9 dB的峰值信噪比和失真比。功耗为34.8，对应的品质因数为0.85 pJ / conv。

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