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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
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A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

机译：用于QC-LDPC卷积码的2.0 Gb / s吞吐量解码器

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摘要

This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10$^{-13}$ at a bit-energy-to-noise power-spectral-density ratio $(E_{b}/N_{0})$ of 3.55 dB.
机译： $ ^ {-13} $ 的出色错误性能，噪声功率谱密度比 $（E_ {b} / N_ {0}）$ 为3.55 dB。

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