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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning
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Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

机译：通过三步唤醒分区将功率门控噪声降至最低

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Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lower bound on the delay overhead irrespective of the duration of the sleep period, and takes no account of the effects of changes in the circuit internal nodes during wake-up on the ground bounce noise. We observed the behavior of internal nodes during the sleep-to-active mode transition and identified three distinct stages. This motivates a three-step turn-on scheme and an associated compact power-gating structure that limits the current flowing through the sleep transistor only while the gated block is metastable, but quickly boosts the power supply rail when there are no short-circuit current paths in the logic. This strongly suppresses power gating noise, and also reduces wake-up time. Simulation results of 16-bit arithmetic logic units in 65-nm CMOS technology show that the proposed technique offers the advantage of a wake-up time that scales with the discharged value (during sleep) of the virtual power rail.
机译：功率门控能够在不牺牲性能的情况下应对低功率纳米技术电路中的亚阈值泄漏。但是，电源门控电路中的模式转换会伴随着较大的浪涌/放电电流，从而在电源和接地轨上产生感应性的反弹噪声。通过逐步导通睡眠晶体管已解决了该问题。但这会在延迟开销上引入固定的下限，而与睡眠周期的持续时间无关，并且不考虑在地面反弹噪声唤醒过程中电路内部节点的变化影响。我们观察了从睡眠到活动模式过渡期间内部节点的行为，并确定了三个不同的阶段。这激励了三步导通方案和相关的紧凑型电源门控结构，该结构仅在门控电路块为亚稳态时限制流过睡眠晶体管的电流，但在没有短路电流时迅速提高电源电压逻辑中的路径。这样可以极大地抑制电源门控噪声，还可以减少唤醒时间。 65 nm CMOS技术中16位算术逻辑单元的仿真结果表明，所提出的技术具有唤醒时间与虚拟电源轨的放电值（在睡眠期间）成比例的优点。

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