Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

Lee S.-C.; Chiu Y.

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Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

机译：Sigma-Delta调制器中电容器不匹配的数字校准

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This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta $(Sigma Delta)$ modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple finite-impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the $Sigma Delta$ loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order $Sigma Delta$ modulators.

机译：本文提出了一种基于电容器误差模型的多位离散时间Σ-Δ调制器中的电容器失配校准技术，其中包括非理想积分器增益误差。该模型可以使用简单的有限冲激响应结构来补偿转换中失配引起的非线性记忆错误。利用单位伪随机噪声（PN）来确定误差系数，并设计了一种模拟域PN去除技术，以最大限度地减少由于$ Sigma Delta $环路中的PN循环而导致的输入信号动态范围损失。行为仿真表明，所提出的方案可以有效补偿一阶和二阶Σ-Δ调制器中的多位电容器失配误差。

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来源
《Circuits and Systems I: Regular Papers, IEEE Transactions on》 |2011年第4期|p.690-698|共9页
作者
Lee S.-C.; Chiu Y.;
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作者单位

Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA;

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正文语种 eng
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关键词
$Sigma Delta$ modulator; adaptive digital calibration; analog-to-digital converter (ADC); capacitor mismatch; digital-to-analog converter (DAC); nonlinearity; test signal;

机译：$ Sigma Delta $调制器;自适应数字校准;模数转换器（ADC）;电容器失配;数模转换器（DAC）;非线性;测试信号;

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1. An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator [J] . Kong-pang Pun, Chiu-sing Choy, Cheong-Fat Chan, IEEE transactions on circuits and systems. II, Express briefs . 2004,第5期

机译：无I / Q不匹配的开关电容复合sigma-delta调制器
2. Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators [J] . Ferragina V., Fornasari A., Gatti U., IEEE transactions on circuits and systems . I , Regular papers . 2004,第12期

机译：时间交错的多径A / D sigma-delta调制器中的增益和失调失配校准
3. A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters [J] . Masanori FURUTA, Shoji KAWAHITO, Daisuke MIYAZAKI IEICE Transactions on Electronics . 2002,第8期

机译：流水线模数转换器电容器不匹配的数字校准技术
4. Mismatch improvement for high image rejection in two path switched-capacitor sigma-delta modulators [C] . Cheng W.T., Pun K.P., Choy C.S., Electron Devices and Solid-State Circuits, 2003 IEEE Conference on . 2003

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5. A new DAC mismatch shaping technique for sigma-delta modulators. [D] . Aboudina, Mohamed Mostafa Saber. 2009

机译：一种针对sigma-delta调制器的新型DAC不匹配整形技术。
6. A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes [O] . Risheng Lv, Weiping Chen, Xiaowei Liu 2018

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7. A fourth-order single-bit switched-capacitor sigma-delta modulator for distributed sensor applications [O] . Simona Brigati, Fabrizio Francesconi, Piero Malcovati, 2015

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Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

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