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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization
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Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization

机译：MIMO检测的格简化：从理论分析到硬件实现

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摘要

The advent of multiple-input–multiple-output (MIMO) techniques has resulted in the generation of new design problems, especially in the baseband processing task of symbol detection. Lattice reduction (LR)-aided detection techniques have emerged as a low-complexity method to achieve the same diversity as the maximum likelihood detector. In this article we explore efficient hardware realization of the complex Lenstra, Lenstra, Lovász (CLLL) LR algorithm. We accomplish this task by first developing an understanding of the complex relationship between algorithm and hardware considerations. After proposing hardware-motivated algorithm modifications, we apply this understanding to the design of a 4$,times,$ 4 CLLL processor for MIMO detection. Hardware realization results on a Xilinx XC4VLX80-12 FPGA demonstrate that the CLLL processor has a throughput of over 3.5 M channel matrices per second, outperforming previously disclosed hardware realizations. In addition, the algorithm modifications and design procedures that we propose are easily applied to larger MIMO system sizes.
机译：多输入多输出（MIMO）技术的出现导致了新的设计问题的产生，特别是在符号检测的基带处理任务中。晶格减少（LR）辅助的检测技术已成为一种低复杂度的方法，可实现与最大似然检测器相同的分集。在本文中，我们探索了复杂的Lenstra，Lenstra，Lovász（CLLL）LR算法的高效硬件实现。我们首先通过对算法和硬件考虑因素之间复杂关系的理解来完成这项任务。在提出了硬件驱动的算法修改建议之后，我们将这种理解应用于用于MIMO检测的4×4 CLLL处理器的设计。在Xilinx XC4VLX80-12 FPGA上的硬件实现结果表明，CLLL处理器的每秒吞吐量超过3.5 M通道矩阵，优于先前公开的硬件实现。此外，我们提出的算法修改和设计程序很容易应用于较大的MIMO系统。

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