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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis
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Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis

机译:多载波比奈奎斯特多收发器:硬件架构和性能分析

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摘要

This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time–frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of fast Fourier transforms (FFTs) for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time–frequency spacing, finite wordlengths and their design tradeoffs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65 nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead.
机译:本文评估了多载波比奈奎斯特(FTN)信令收发器的硬件方面。为了提高带宽效率,在FTN系统中选择符号的时频间隔是针对有效的硬件实现。这项工作提出了用于实现FTN多载波调制信号的迭代解码的硬件体系结构。已经考虑了与现有系统的兼容性,以在比奈奎斯特更快的速率和正交信令方案之间进行平滑切换。一种就是使用快速傅里叶变换(FFT)进行多载波调制。定点模型的性能非常接近浮点表示。已经研究了系统参数(如投影点数量,时频间隔,有限字长及其设计折衷)对降低FTN系统中复杂度的迭代解码器的影响。 FTN解码器已在65 nm CMOS和FPGA中设计和合成。从硬件资源使用数量可以得出结论,FTN信令可用于以可接受的复杂性开销实现更高的带宽效率。

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