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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters
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A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters

机译：完全集成且可重新配置的架构，用于高速模数转换器的相干自检

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摘要

This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 $mu{hbox {m}}$ CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology.
机译：本文提出了一种可重构架构，用于具有中等分辨率的高速模数转换器（ADC）的相干内置自检（BIST）。拟议的系统适合与ADC完全集成，并且除了低抖动时钟基准外，不需要其他外部高质量发生器。完整的系统包括两个同步锁相环（PLL），一个基于能够提供低失真输出的两个积分器振荡器，另一个基于能够提供低抖动平方输出的张弛振荡器，以允许相干采样。给出了两个PLL的构建模块的详细说明，以及用于使环路滤波器（LF）的面积最小化，将两个积分器振荡器的输出幅度稳定到已知值并改善总和的技术。该振荡器的谐波失真（THD）。使用0.13 $ mu {hbox {m}} $ CMOS技术进行的布局后仿真图中显示了一个用于案例研究的6位1 GS / s ADC，并验证了所提出的测试方法。

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