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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Reduction of Substrate Noise in Sub Clock Frequency Range
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Reduction of Substrate Noise in Sub Clock Frequency Range

机译：在子时钟频率范围内降低基板噪声

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We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.
机译：我们提出一种减少集成电路基板中的开关噪声的方法。主要思想是设计数字电路以获得与时钟相同周期的周期性电源电流。此属性将开关噪声的频率成分定位在时钟频率以上。差分归零信令用于减少电流的数据相关性。电路通过带有内部异步D寄存器的对称预充电DCVS逻辑实现。芯片是采用标准的130 nm CMOS技术制造的，具有两个版本的流水线16位加法器。第一个版本使用建议的方法，第二个版本使用常规的静态CMOS逻辑电路和TSPC寄存器。相应的设备数量为1190和684，最大工作频率为450和375 MHz。频域测量是在基片节点上使用片上生成的正弦和伪随机数据以300 MHz的时钟频率进行的。正弦波情况导致最大的频率分量，其中所建议的电路的最大功率降低了8.5 dB / Hz，而功耗却是原来的三倍。

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