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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range
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FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range

机译：具有1.58 ps分辨率和59.3分钟工作范围的FPGA Vernier数模转换器

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摘要

The first FPGA multiple channel digital-to-time converter, or digital pulse generator, is proposed to further extend FPGA applications into analog domain. Based on vernier principle, the effective resolution is made equivalent to the period difference of two phase-locked loop (PLL) outputs. The finer than ever DTC resolution of 1.58 ps is achieved with an Altera Stratix III FPGA chip. The DNL and INL are verified to be $-0.086sim +0.12~{rm LSB}$ and $-0.93sim +0.75~{rm LSB}$ respectively for input value varied from 1 to 1026. The widest operation range of 59.3 minutes is accomplished with 51 functioning input bits. Except for 2 shared PLLs, there are only 422 combinational ALUTs and 84 dedicated logic registers utilized per channel for 224-channel circuit implementation. The power consumption per channel is simulated to be 3.04 mW only. With a simple but powerful structure, the design cost is substantially reduced from those of its predecessors .
机译：提出了第一个FPGA多通道数字至时间转换器或数字脉冲发生器，以进一步将FPGA应用扩展到模拟域。根据游标原理，使有效分辨率等于两个锁相环（PLL）输出的周期差。使用Altera Stratix III FPGA芯片可实现比以往任何时候都更好的1.58 ps的DTC分辨率。对于输入值从1到1026的变化，DNL和INL分别被验证为$ -0.086sim + 0.12〜{rm LSB} $和$ -0.93sim + 0.75〜{rm LSB} $。最大操作范围为59.3分钟用51个功能输入位完成。除2个共享PLL外，每个通道仅使用422个组合ALUT和84个专用逻辑寄存器来实现224通道电路。每个通道的功耗仅模拟为3.04 mW。凭借简单但功能强大的结构，与前代产品相比，其设计成本已大大降低。

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