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首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
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Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

机译：适用于高速SerDes应用的低功耗可编程伪随机字发生器和时钟乘法器单元

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This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of $2 ^{7} -1$, $2 ^{10} -1$, $2 ^{15} -1$, $2 ^{23} -1$, and $2 ^{31} -1~hbox{b}$ according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ${hbox {ps}}_{rm rms}$, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-$mu{hbox {m}}$ CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.
机译：本文介绍了用于高速SerDes应用的低功耗可编程伪随机字发生器（PRWG）和低噪声时钟乘法器单元（CMU）的设计。 PRWG能够生成序列长度为$ 2 ^ {7} -1 $，$ 2 ^ {10} -1 $，$ 2 ^ {15} -1 $，$ 2 ^ {23} -1 $和$ 2的测试模式^ {31} -1〜hbox {b} $根据CCITT建议，随机字为16位宽。 PRWG的高速和低功耗操作是通过并行反馈技术实现的。 CMU的测量抖动仅为3.56 $ {hbox {ps}} _ {rm rms} $，PRWG输出的数据抖动主要由CMU确定。通过采用0.18-μM的CMOS工艺实现，PRWG的功耗仅为10.8 mW，CMU从1.8 V电源消耗的功率约为87 mW。该PRWG可以用作外部并行测试图生成器的低成本替代品。

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