A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

Ortmanns M.; Gerfers F.; Manoli Y.

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A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

机译：连续时间/ spl Sigma // spl Delta /调制器，通过SCR反馈降低了对时钟抖动的敏感性

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This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.

机译：本文提出了一种在连续时间反馈数字调制器中使用带有电阻元件的改进型开关电容器结构，以克服连续时间sigma-delta（/ spl Sigma // spl Delta /）调制器对时钟抖动的高灵敏度的方法。模拟转换器（DAC）。降低的抖动敏感性既可以通过两个已实现的三阶调制器的测量结果进行仿真，也可以得到验证。此外，通过分析和仿真来分析非理想行为。

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来源
《IEEE Transactions on Circuits and Systems. I, Regular Papers》 |2005年第5期|p.875-884|共10页
作者
Ortmanns M.; Gerfers F.; Manoli Y.;
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原文格式 PDF
正文语种 eng
中图分类 TN71;
关键词
circuit feedback; circuit simulation; clocks; digital-analogue conversion; jitter; sensitivity; sigma-delta modulation; switched capacitor networks; clock jitter; continuous-time feedback digital-analog converter; sensitivity; sigma-delta modulator; switched-capacit;

机译：电路反馈;电路仿真;时钟;数模转换;抖动;灵敏度;sigma-delta调制;开关电容网络;时钟抖动;连续时间数模转换器;灵敏度;sigma-delta调制器;开关电容;

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专利

1. Signal-dependent timing jitter in continuous-time /spl Sigma//spl Delta/ modulators [J] . Cherry J.A., Snelgrove W.M. Electronics Letters . 1997,第13期

机译：连续时间/ spl Sigma // spl Delta /调制器中与信号有关的时序抖动
2. A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback [J] . Dejan Radjen, Pietro Andreani, Martin Anderson, Analog Integrated Circuits and Signal Processing . 2013,第1期

机译：通过DSCR反馈降低时钟抖动灵敏度的连续时间delta-sigma调制器
3. Continuous-time delta-sigma modulator using vector filter in feedback path to reduce effect of clock jitter and excess loop delay [J] . Yuki Kimura, Akira Yasuda, Michitaka Yoshino Analog Integrated Circuits and Signal Processing . 2013,第2期

机译：在反馈路径中使用矢量滤波器的连续时间delta-sigma调制器，以减少时钟抖动和过多环路延迟的影响
4. A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS [C] . Paton, S., Di Giandomenic, . 2004

机译：12位连续时间/ spl Sigma // spl Delta /调制器，具有400MHz时钟，在0.13 / spl mu / m CMOS中具有低抖动灵敏度
5. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator [D] . Rashidi, Negar. 2016

机译：低噪声，抖动耐受连续时间Sigma-Delta调制器
6. A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate [O] . Yao Xiao, Zhifei Lu, Zhaofeng Ren, 2020

机译：具有2.4Ghz时钟速率的100Mhz带宽80dB动态范围连续时间Δ-Σ调制器
7. Continuous-time delta-sigma modulator using vector filter in feedback path to reduce effect of clock jitter and excess loop delay [O] . 2013

机译：在反馈路径中使用矢量滤波器的连续时间delta-sigma调制器，以减少时钟抖动和过多环路延迟的影响

A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

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