Voltage-mode CMOS chaos generator and observation of internalstates with a bitmap memory

Takakubo H.; Takakubo K.; Mangaser R.A.; Shono K.

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Voltage-mode CMOS chaos generator and observation of internalstates with a bitmap memory

机译：电压模式CMOS混沌发生器和带位图存储器的内部状态观察

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摘要

A feedback circuit consisting of a three-stage array of weighted CMOS inverters, two CMOS transmission gates and a holding capacitance generates chaos. Trajectories can be designed from the transfer characteristics of the three-stage array of weighted CMOS inverters, which directly produces a nonlinear mapping function. The chaotic trajectories were observed via a bitmap display

机译：由三级加权CMOS反相器阵列，两个CMOS传输门和一个保持电容组成的反馈电路会产生混乱。可以根据加权CMOS反相器的三级阵列的传输特性来设计轨迹，这可以直接产生非线性映射函数。通过位图显示观察到混沌轨迹

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《IEEE Transactions on Circuits and Systems. I, Regular Papers》 |1994年第11期|p.759-762|共4页
作者
Takakubo H.; Takakubo K.; Mangaser R.A.; Shono K.;
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原文格式 PDF
正文语种 eng
中图分类 TN71;
关键词
CMOS digital integrated circuits; bifurcation; bit-mapped graphics; chaos; circuit feedback; signal generators; CMOS transmission gates; bitmap display; bitmap memory; chaotic trajectories; feedback circuit; holding capacitance; internal states observation; nonlinear;

机译：CMOS数字集成电路;分叉;位图图形;混沌;电路反馈;信号发生器;CMOS传输门;位图显示;位图存储器;混沌轨迹;反馈电路;保持电容;内部状态观察;非线性;

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1. Voltage-mode CMOS chaos generator and observation of internal states with a bitmap memory [J] . Takakubo H., Takakubo K. IEEE Transactions on Circuits and Systems. 1 . 1994,第11期

机译：电压模式CMOS混沌发生器和带位图存储器的内部状态观察
2. A family of fully integrated CMOS chaos generators with strictly 1 -D linear-piecewise chaos maps [J] . Nguyen Van Ha, Kumar Sandeep, Song Hanjung Journal of Computational Electronics . 2018,第3期

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3. STATISTICAL TESTING OF A CHAOS BASED CMOS TRUE-RANDOM NUMBER GENERATOR [J] . FABIO PARESCHI, rnGIANLUCA SETTI, rnRICCARDO ROVATTI Journal of circuits, systems and computers . 2010,第4期

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Voltage-mode CMOS chaos generator and observation of internalstates with a bitmap memory

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