Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

Allstot D.J.; San-Hwa Chee

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Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

机译：适用于低噪声混合信号IC的折叠式源极耦合逻辑与CMOS静态逻辑

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CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing ( Delta V/sub L/ approximately=0.2 V/sub dd/) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2- mu m CMOS process, and simulated results with a standard 1- mu m process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies.

机译：与传统的静态逻辑相比，CMOS折叠式源极耦合逻辑（FSCL）使用较小的逻辑电压摆幅（Delta V / sub L /大约= 0.2 V / sub dd /），并在高工作频率下实现了较小的功率延迟乘积。通过在全差分FSCL电路中使用电流控制技术来维持恒定的电源电流，与传统的CMOS静态逻辑相比，数字开关噪声可降低30-300倍。给出了在2微米CMOS工艺中制造的FSCL栅极的测量结果，并使用标准1微米工艺的仿真结果来比较FSCL和5.0-，静态逻辑的功率，延迟和开关噪声特性， 3.3V和2.0V电源。

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《IEEE Transactions on Circuits and Systems. 1》 |1993年第9期|P.553-563|共11页
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Allstot D.J.; San-Hwa Chee;
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1. Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits [J] . Kundan J., Hasan S.M.R. IEEE Transactions on Circuits and Systems. II . 2000,第8期

机译：用于低压混合信号集成电路的增强型折叠式源极耦合逻辑技术
2. Synthesis techniques for CMOS folded source-coupled logic circuits [J] . Maskai S.R., Kiaei S. IEEE Journal of Solid-State Circuits . 1992,第8期

机译：CMOS折叠式源极耦合逻辑电路的合成技术
3. Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic [J] . Abdul Sajid, Ahmad Nafees, Saifur Rahman International Journal of Information Technology and Computer Science . 2013,第11期

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4. Current mode BiCMOS folded source-coupled logic circuits [C] . Kundan, J., Rezaul Asan, . 1997

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Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

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