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首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits
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A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits

机译：用于vLSI电路的虚拟穷举测试的协调电路划分和测试生成方法

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摘要

In this paper, we present a circuit partitioning and test pattern generation technique for pseudo-exhaustive built-in self-testing of VLSI circuits. The circuit partitioning process divides a given circuit into a set of subcircuits which can be exhaustively tested, while the test pattern generation process generates reduced exhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). In conventional approaches, these two problems are considered separately. However, in this paper, both problems are considered and solved in the same phase. A graph theoretic model of VLSI circuits is proposed. Based on this model, a circuit partitioning algorithm using the concept of minimum vertex cut is devised to partition the circuit into a set of exhaustively testable subcircuits with restricted hardware overhead. Each time a subcircuit is generated by the partitioning algorithm, the test pattern generation problem is considered. A new algorithm, based on the subcircuit modification technique, is proposed with the objective of generating reduced exhaustive test patterns of limited length (e.g., /spl les/2/sup 20/) using LFSR's, for each of the subcircuits. This task is embedded in the circuit partitioning process itself, leading to an efficient and well-coordinated solution. Experiments using ISCAS benchmark circuit simulation have been conducted. The results demonstrate that the proposed method is very good.
机译：在本文中，我们提出了一种用于虚拟穷举内置VLSI电路自测试的电路划分和测试模式生成技术。电路划分过程将给定电路划分为一组可以进行详尽测试的子电路，而测试模式生成过程则使用线性反馈移位寄存器（LFSR）为每个子电路生成精简的详尽测试模式。在常规方法中，这两个问题是分开考虑的。但是，在本文中，这两个问题都是在同一阶段考虑和解决的。提出了VLSI电路的图形理论模型。基于此模型，设计了一种使用最小顶点割的概念的电路划分算法，以将电路划分为一组可穷尽测试的子电路，且硬件开销有限。每次通过分割算法生成子电路时，都会考虑测试模式生成问题。提出了一种基于子电路修改技术的新算法，其目的是为每个子电路使用LFSR生成有限长度的简化穷举测试模式（例如，/ spl les / 2 / sup 20 /）。这项任务被嵌入到电路划分过程中，从而产生了一个高效且协调良好的解决方案。已经进行了使用ISCAS基准电路仿真的实验。结果表明，该方法是很好的。

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