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首页> 外文期刊>IEEE transactions on dependable and secure computing >Reducing Timing Side-Channel Information Leakage Using 3D Integration
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Reducing Timing Side-Channel Information Leakage Using 3D Integration

机译：使用3D集成减少时序侧信道信息泄漏

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摘要

Recently, following the work pioneered by Kocher [1], using cache behavior as a timing side-channel to leak critical system information has received lots of attentions because of its easy-to-implement nature and amazingly good results. Recent attacks have been demonstrated to successfully leak the full key from many commonly used encryption algorithms including RSA, AES, etc. These attacks pose great threats to applications that depend on these encryption methods such as banking systems, military systems, etc. To mitigate the increasing threat, numerous countermeasures, mostly software patches, have been proposed. Hardware mitigations, however, have been less pursued. 3D integration, which stacks multiple dies vertically, offers shorter wire-length and improves system performance. It may be used to offset the performance overhead these countermeasures incur. In this paper, we investigate several possible ways in which the availability of 3D integration can be exploited to mitigate timing side-channel attacks while still obtaining superior performance over a baseline 2D system. Simulation results using Gem5 simulator show that our techniques can significantly reduce timing information leakage while still achieving 20.43 percent performance gain over a 2D baseline system.
机译：最近，遵循Kocher [1]的开创性工作，使用缓存行为作为定时侧通道泄漏关键系统信息已受到广泛关注，因为它具有易于实现的特性和令人惊讶的良好结果。事实证明，最近的攻击成功地从许多常用的加密算法（包括RSA，AES等）中泄漏了完整密钥。这些攻击对依赖这些加密方法的应用程序（如银行系统，军事系统等）构成了严重威胁。威胁日益严重，已经提出了许多对策，主要是软件补丁。但是，对硬件的缓解却很少。 3D集成可垂直堆叠多个管芯，从而缩短了导线长度并提高了系统性能。它可以用来抵消这些对策带来的性能开销。在本文中，我们研究了几种可能的方式，在这些方式中，可以利用3D集成的可用性来缓解定时侧信道攻击，同时仍然获得优于基准2D系统的性能。使用Gem5模拟器进行的仿真结果表明，我们的技术可以显着减少时序信息泄漏，同时在2D基准系统上仍可实现20.43％的性能提升。

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